1. Field of the Invention
The present invention relates generally to capacitors, and in particular to capacitors that are implemented within a semiconductor device.
2. Discussion of the Related Art
Conventional capacitors that are fabricated on semiconductor devices for storing charge are typically configured as metal-to-metal capacitors (MOMs). Referring to FIG. 1, the construction of a typical MOM 10 is illustrated. The MOM 10 includes two electrodes 12 that are formed on conductor layers 14 and 16 that are separated by a dielectric 18. A substrate 19 forms a base for the MOM 10. In addition to the device capacitance which is formed between the electrodes, there is also an undesirable parasitic capacitance that is formed between the substrate 19 and adjacent electrode. In many conventional devices, the parasitic capacitance may exceed 20% of the value of the capacitance between the electrodes of the capacitor. To increase the value of capacitance, generally either the plate area of the MOM is increased, or the dielectric thickness is decreased. Both of these options have drawbacks. Increasing the plate area causes a further undesirable increase in the parasitic capacitance, while reducing the dielectric thickness requires an extra process step that significantly increases the cost of the device. In addition, the matching characteristics of conventional semiconductor capacitors are deficient due to the non-symmetrical effect of external fields on adjacent capacitors.